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Assembly Language
coprocessor and multiprocessor operations
summary
This web page examines multiprocessor and coprocessor instructions in assembly language. Specific examples of instructions from various processors are used to illustrate the general nature of assembly language.
For those with high speed connections, the very large single file summary is still on line.
coprocessor and multiprocessor operations
Multiprocessor instructions are used to coordinate activity between multiple processors.
Some multiprocessor instructions are designed to allow the processors to communicate with each other. A test and set instruction is used to implement flags or semaphores between processors. A compare and swap instruction is used to implement more sophsticated communications between multiple processors (such as counters or queue pointers) or secure updates of shared system control data structures in a multi-processing environment. Interlocked instructions are used to update counters, flags, and semaphores while locking out any other processors or devices from changing or reading the memory location while it is being updated.
- TAS Test and Set an Operand; Motorola 680x0; tests the current value of the operand at the effective address in memory or a data register (obviously, data register operands aren’t multiprocessor, but the instruction still works) and sets or clears the N (negative) and Z (zero) condition codes accordingly, then sets the high order bit of the operand to one; this operation uses a read-modify-write memory cycle that completes the operation without interruption; sets or clears flags
- CAS Compare and Swap with Operand; Motorola 680x0; Compares the operand at an effective address in memory to a compare operand in a data register, if the operands are equal, the update operand is transferred from a data register to the original effective address, if the operands are unequal, the operand at the effective address is transferred to the data register that contained the compare operand; this operation uses a read-modify-write memory cycle that completes the operation without interruption; sets or clears flags
- CAS2 Dual Operand Compare and Swap; Motorola 680x0; Compares the operand at an effective address in memory to a compare operand in a data register, if the operands are equal, compares the operand at a second effective address in memory to a second compare operand in a data register, if the second operand is also equal, the update operands are transferred from a data register to the pair of original effective addresses, if either pair of operands are unequal, the operands at the pair of effective addresses are transferred to the data registers that contained the compare operands; this operation uses a read-modify-write memory cycle that completes the operation without interruption; sets or clears flags
- ADAWI Add Aligned Word Interlocked; DEC VAX; adds (16 bit integer) a source operand from a register or memory to a memory location that is word aligned while interlocking the memory location so that no other processor or device can read or write to the interlocked memory location, used to maintain operating system resource usage counts; and sets or clears flags
- INSQHI Insert Entry into Queue at Head, Interlocked; DEC VAX; inserts a forward and backward linked entry into the head of a queue, checking first that all memory accesses can be performed without memory management exception, uses interlock to allow a queue to be shared by multiple prcoesses even in a multiprocessor environment without any additional synchronization
- INSQTI Insert Entry into Queue at Tail, Interlocked; DEC VAX; inserts a forward and backward linked entry into the tail of a queue, checking first that all memory accesses can be performed without memory management exception, uses interlock to allow a queue to be shared by multiple prcoesses even in a multiprocessor environment without any additional synchronization
- REMQHI Remove Entry from Queue at Head, Interlocked; DEC VAX; removes a forward and backward linked entry from the head of a queue, checking first that all memory accesses can be performed without memory management exception, uses interlock to allow a queue to be shared by multiple prcoesses even in a multiprocessor environment without any additional synchronization
- INSQTI Remove Entry from Queue at Tail, Interlocked; DEC VAX; removes a forward and backward linked entry from the tail of a queue, checking first that all memory accesses can be performed without memory management exception, uses interlock to allow a queue to be shared by multiple prcoesses even in a multiprocessor environment without any additional synchronization
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Created: February 21, 2001 (from machcode.htm)
Last Updated: December 1, 2010
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